Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic

Minkyu SONG  Kunihiro ASADA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E81-C   No.11   pp.1740-1749
Publication Date: 1998/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
power saved pass-transistor logic (PSPL),  low power,  regenerative feedback,  5454-bit multiplier,  7-bit serial counter,  

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Summary: 
In this paper, a novel pass-transistor logic with an efficient level restoration circuit, named Power Saved Pass-transistor Logic (PSPL), is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of PSPL, a 5454-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth Encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13. 5 ns in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. Furthermore, a sequential circuit of a low power 7-bit serial counter is designed and fabricated in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. The measured operating speed was 250 MHz.