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A New Broadband Buffer Circuit Technique and Its Application to a 10-Gbit/s Decision Circuit Using Production-Level 0. 5 µm GaAs MESFETs
Miyo MIYASHITA Naoto ANDOH Kazuya YAMAMOTO Junichi NAKAGAWA Etsuji OMURA Masao AIGA Yoshikazu NAKAYAMA
IEICE TRANSACTIONS on Electronics
Publication Date: 1998/10/25
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
GaAs MESFET, buffer circuit, decision circuit, peaking inductor, source-follower,
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A new broadband buffer circuit technique and its analytical design method are proposed for a high-speed decision circuit featuring both a higher input sensitivity and a larger phase margin. The buffer circuit characteristics are significantly improved by employing a series peaking source follower (SPSF), where a peaking inductor is inserted between the first and second source follower stages. Optimization of the peaking inductance successfully enhances the 3-dB bandwidth of the data-input buffer and the clock buffer by 7 GHz for both, over conventional double-stage source follower SCFL buffers. The proposed circuit technique and design method are applied to a 10-Gbit/s decision circuit by the use of production-level 0. 5 µm GaAs MESFETs. The fabricated decision circuit achieves a data input sensitivity of 43 mVp-p and a phase margin of 240 both at 10-Gbit/s: a 230 mVp-p smaller input sensitivity and a 35 larger phase margin than those of conventional non-peaking inductor types.