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Design Considerations of Data-Driven Self-Timed RSFQ Adder Circuits
Nobuyuki YOSHIKAWA Hiroshi TAGO Kaoru YONEYAMA
IEICE TRANSACTIONS on Electronics
Publication Date: 1998/10/25
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Low- and High-Temperature Superconductive Electron Devices and Their Applications)
Category: Digital Applications
RSFQ logic circuits, single flux quantum, superconducting circuits, high-speed integrated circuits, adder,
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We have designed rapid single-flux-quantum (RSFQ) adder circuits using two different architectures: one is the conventional architecture employing globally synchronous clocking and the other is the data-driven self-timed (DDST) architecture. It has been pointed out that the timing margin of the RSFQ logic is very sensitive to the circuit parameter variations which are induced by the fabrication process and the device parameter uncertainty. Considering the physical timing in the circuits, we have shown that the DDST architecture is advantageous for realizing RSFQ circuits operating at very high frequencies. We have also calculated the theoretical circuit yield of the DDST adders and shown that a four-bit system operating at 10 GHz is feasible with sufficient operating margin, considering the present 1 kA/cm2 Nb Josephson technology.