Design and Evaluation of Scalable Shared-Memory ATM Switches

Mohammad ALIMUDDIN  Hussein M. ALNUWEIRI  

Publication
IEICE TRANSACTIONS on Communications   Vol.E81-B   No.2   pp.224-236
Publication Date: 1998/02/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on ATM Switching Systems for future B-ISDN)
Category: ATM switching architecture
Keyword: 
ATM switch,  truncated Banyan architecture,  dilation,  shared-memory,  bursty traffic,  LC backpressure,  

Full Text: PDF>>
Buy this Article




Summary: 
This paper proposes a number of simple, yet very effective, cell switching architectures that employ shared memory as a basic switching component. Employing small shared-memory switching has several major advantages. First, by taking advantage of commercially available memory technologies, ATM switch design can be simplified to determining a suitable shared-memory module size, and identifying a proper interconnection among the modules. In this way, switch architectures can be reusable and able to evolve as memory technology advances. Second, shared memory greatly enhances buffer space utilization, allows the implementation of flexible and fair buffer allocation policies for multiple services. The switch architectures presented in this paper offer a number of alternative shared buffering schemes including, shared output, input with shared output, and multistage shared buffering. The proposed architectures employ simple, self-routing, interconnection fabrics. We present several simulation results that demonstrate the superior performance of our switch architectures under uniform, bursty, and non-uniform (or hot-spot) input traffic.