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A VLSI Architecture Design for Dual-Mode QAM and VSB Digital CATV Transceiver
Muh-Tian SHIUE Chorng-Kuang WANG Winston Ingshih WAY
IEICE TRANSACTIONS on Communications
Publication Date: 1998/12/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the Latest Development of Telecommunication Research)
Category: Wireless Communication Systems
QAM, VSB, AGC, carrier recovery, timing recovery, fractionally spaced blind equalizer and DFE,
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In this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are 6 kHz of carrier frequency offset, 110 ppm of symbol rate offset, and -82 dBc carrier phase-jitter at 10 kHz away from the nominal carrier frequency.