A Pin Assignment and Global Routing Algorithm for Floorplanning

Takahiro SHIOHARA  Masahiro FUKUI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E81-A   No.8   pp.1725-1732
Publication Date: 1998/08/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
floorplan,  pin assignment,  global route,  maximum flow algorithm,  

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In this paper, we present a hierarchical technique for simultaneous pin assignment and global routing during floorplanning based on the minimum cost maximum integer flow algorithm with several heuristic cost functions. Furthermore, our algorithm handles feedthrough pins and equi-potential pins taking into account global routes. Our algorithm allows various user specified constraints such as pre-specified pin positions, wiring paths, wiring widths and critical nets. Experimental results including Xerox floorplanning benchmark have shown the effectiveness of the heuristics.