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A Low-Power DSP Core Architecture for Low Bitrate Speech Codec
Hiroyuki OKUHATA Morgan H. MIKI Takao ONOYE Isao SHIRAKAWA
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E81-A
No.8
pp.1616-1621 Publication Date: 1998/08/25 Online ISSN:
DOI: Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: G. 723. 1, VLSI, DSP, low-power, speech codec,
Full Text: PDF>>
Summary:
A VLSI implementation of a low-power DSP core is described, which is dedicated to the G. 723. 1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory. The main attempt is focused on lowering the clock frequency, and therefore on reducing the total power consumption, at the cost of a fairly small increase of chip area. The proposed DSP architecture has been integrated in the total area of 7. 75 mm2 by using a 0. 35 µm CMOS technology, which can operate at 10 MHz with the dissipation of 44. 9 mW from a single 3 V supply.
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