Design of a Digital Chaos Circuit with Nonlinear Mapping Function Learning Ability

Kei EGUCHI  Takahiro INOUE  Akio TSUNEDA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E81-A   No.6   pp.1223-1230
Publication Date: 1998/06/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Nonlinear Problems
Keyword: 
chaos circuits,  neuro-fuzzy circuits,  supervised learning,  discrete-time circuits,  digital circuits,  integrated circuits,  

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Summary: 
In this paper, an FPGA (Field Programmable Gate Array)-implementable digital chaos circuit with nonlinear mapping function learning ablility is proposed. The features of this circuit are user-programmability of the mapping functions by on-chip supervised learning, robustness of chaos signal generation based on digital processing, and high-speed and low-cost thanks to its FPGA implementation. The circuit design and analysis are presented in detail. The learning dynamics of the circuit and the quantitization effect to the quasi-chaos generation are analyzed by numerical simulations. The proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This confirmed that the one-dimensional chaos circuit block (except for SRAM's) is implementable on a single FPGA chip and can generate quasi-chaos signals in real time.