Unified Tag Memory Architecture with Snoop Support

Yonghwan LEE  Wookyeong JEONG  Yongsurk LEE  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E81-A   No.6   pp.1172-1175
Publication Date: 1998/06/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section of Papers Selected from ITC-CSCC'97)
Category: Systems and Control
unified tag,  cache tag,  TLB,  VLSI,  

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A unified tag by which both TLBs and caches can be accessed is presented. This architecture reduces the chip area of conventional cache tags and also improves the speed of cache systems. In addition, it has expanded to support snoop accesses for multiprocessor environments. To validate the proposed architecture, we measured the area and speed based on VLSI circuits.