Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load

Hidetoshi ONODERA
Keikichi TAMARU

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E81-A    No.3    pp.462-469
Publication Date: 1998/03/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems)
short-circuit power dissipation,  short-circuit current,  resistive-capacitive load,  CRC π load,  output waveform,  gate delay,  

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As MOSFET sizes and wire widths become very small in recent years, influence of resistive component of interconnects on the estimation of propagation delay and power dissipation can no longer be neglected. In this paper we present formulas of output waveform at driving point and short-circuit power dissipation for static CMOS logic gates driving a CRC π load. By representing the short-circuit current and the current flowing in the resistance of a CRC π load by piece-wise linear functions, a closed-form formula is derived. On the gate delay the error of our formula is less than 8% from SPICE in our experiments. These formulas will contribute to faster estimation of circuit speed and power dissipation of VLSI chips on timing level simulators.