Design of a Sub-1. 5 V, 20 MHz, 0. 1% MOS Current-Mode Sample-and-Hold Circuit

Yasuhiro SUGIMOTO  Masahiro SEKIYA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E81-A   No.2   pp.258-260
Publication Date: 1998/02/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)
Category: 
Keyword: 
low voltage,  high speed,  high accuracy,  MOS analog circuit,  sample-and-hold circuit,  

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Summary: 
This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.