Analog Circuit Design Methodology in a Low Power RISC Microprocessor

Koichiro ISHIBASHI  Hisayuki HIGUCHI  Toshinobu SHIMBO  Kunio UCHIYAMA  Kenji SHIOZAWA  Naotaka HASHIMOTO  Shuji IKEDA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E81-A   No.2   pp.210-217
Publication Date: 1998/02/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: INVITED PAPER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)
Category: 
Keyword: 
microprocessor,  TLB,  CAM,  0. 35 µm,  CMOS,  

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Summary: 
There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96- mm 2 test chip with the super H architecture using 0. 35-µm four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2. 0-W power dissipation.