Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches

Hiroyuki TOMIYAMA  Tohru ISHIHARA  Akihiko INOUE  Hiroto YASUURA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E81-A    No.12    pp.2621-2629
Publication Date: 1998/12/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Compiler
compiler optimization,  instruction scheduling,  low power,  caches,  

Full Text: PDF(762.4KB)>>
Buy this Article

In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.