Dual-Loop Digital PLL Design for Adaptive Clock Recovery

Tae Hun KIM  Beomsup KIM  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E81-A   No.12   pp.2509-2514
Publication Date: 1998/12/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Transistor-level Circuit Analysis, Design and Verification
Keyword: 
digital PLL,  DPLL,  PLL,  adaptive algorithm,  clock recovery,  

Full Text: PDF(638.8KB)>>
Buy this Article




Summary: 
Since most digital phase-locked loops (DPLLs) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady-state, the DPLL loop bandwidth is preferred to being adjusted accordingly. In this paper, a bandwidth adjusting (adaptive) algorithm is presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. This algorithm, based on the recursive least squares (RLS) criterion, suggest an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithm can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drivers that require a short initial preamble period.