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An Algorithm for Estimating Bottleneck Effect in Series-Parallel Tree Circuits
Molin CHANG Wang-Jin CHEN Jyh-Herng WANG Wu-Shiung FENG
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/11/25
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
waveform-based switch-level timing simulator, slope estimation, bottleneck effect,
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The slope of transient waveform is dominated by the characteristics of the discharging (or charging) path, including the path topology, the sizes and the states of MOS transistors. The slope value of transient waveform can be obtained by calculating the equivalent RC time constant of the evaluated cluster circuit, and it can be obtained efficiently by traversing the tree recursively. However, bottleneck effect always exists in the charging/discharging path and plays an important role on the charging/discharging behavior of the output. If neglect the effect, the waveform approximation technique used in BTS will give rise to a larger error in some cases. Therefore, we propose an algorithm to solve this problem.