IEICE Trans - Achieving Fault Tolerance in Pipelined Multiprocessor Systems

Achieving Fault Tolerance in Pipelined Multiprocessor Systems

Jeng-Ping LIN  Sy-Yen KUO

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E80-D   No.6   pp.665-671
Publication Date: 1997/06/25
Online ISSN:
DOI:
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerant Computing
Keyword:
precise computation state,  error recovery,  checkpoint,  pipelined machine,  multiprocessor,

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Summary:
This paper focuses on recovering from processor transient faults in pipelined multiprocessor systems. A pipelined machine may employ out of order execution and branch prediction techniques to increase performance, thus a precise computation state would not be available. We propose an efficient scheme to maintain the precise computation state in a pipelined machine. The goal of this paper is to implement checkpointing and rollback recovery utilizing the technique of precise interrupt in a pipelined system. Detailed analysis is included to demonstrate the effectiveness of this method.