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Design of Array Processors for 2-D Discrete Fourier Transform
Shietung PENG Igor SEDUKHIN Stanislav SEDUKHIN
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/04/25
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Parallel and Distributed Supercomputing)
algorithm mapping, 2-dimensional discrete Fourier transform, parallel processing, systolic array processors, VLSI architectures,
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In this paper the design of systolic array processors for computing 2-dimensional Discrete Fourier Transform (2-D DFT) is considered. We investigated three different computational schemes for designing systolic array processors using systematic approach. The systematic approach guarantees to find optimal systolic array processors from a large solution space in terms of the number of processing elements and I/O channels, the processing time, topology, pipeline period, etc. The optimal systolic array processors are scalable, modular and suitable for VLSI implementation. An application of the designed systolic array processors to the prime-factor DFT is also presented.