Statechart Methodology for the Design, Validation, and Synthesis of Large Scale Asynchronous Systems

Rakefet KOL  Ran GINOSAR  Goel SAMUEL  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E80-D   No.3   pp.308-314
Publication Date: 1997/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Asynchronous Circuit and System Design)
Category: Specification Description
Keyword: 
asynchronous logic design,  statechart,  validation,  synthesis,  

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Summary: 
We apply a novel methodology, based on statecharts, to the design of large scale asynchronous systems. The design is specified at multiple levels, simulated, animated, and compiled into synthesizable VHDL code by using the ExpressV-HDL CAD tool. We add a validation sub-system to chech correct operation. ExpressV-HDL is originally synchronous, but we employ it for asynchronous design by avoiding any design dependence on the clock, and simulating with fast clock and on-line delays. The tool is demonstrated through a simple FSM. The synthesized synchronous circuit can be converted into an asynchronous one. Some results of a post-synthesis conversion example are given.