Address Addition and Decoding without Carry Propagation

Yung-Hei LEE  Seung Ho HWANG  

IEICE TRANSACTIONS on Information and Systems   Vol.E80-D   No.1   pp.98-100
Publication Date: 1997/01/25
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Algorithm and Computational Complexity
decoding,  cache memory,  memory latency,  pipelined architecture,  parallel adders,  carry propagation,  

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The response time of adders is mainly determined by the carry propagation delay. This letter deals with a scheme which combines the address addition and decoding together. Although addition is involved in the process, we show that it can be computed without carry propagation. Memory latency is one of the most performance limiting factors. The authors present a new decoder logic named fused add-decoder (FADEC), which performs address addition and decoding in a single process. FADEC can reduce memory latency by eliminating separate address addition cycle.