Quad-Processor Redundancy for a RISC-Based Fault Tolerant Computer

Shinichiro YAMAGUCHI  Tetsuaki NAKAMIKAWA  Naoto MIYAZAKI  Yuuichirou MORITA  Yoshihiro MIYAZAKI  Sakou ISHIKAWA  

IEICE TRANSACTIONS on Information and Systems   Vol.E80-D   No.1   pp.15-20
Publication Date: 1997/01/25
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Redundancy Techniques
fault tolerance,  fault tolerant computer,  redundant system,  dual system,  high availability,  UNIX,  RISC,  transaction processing,  open system,  

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The fault tolerant computer (FTC) is applied as a communication or database server in the information service and computer aided process control fields. User requires of the FTC are to provide the current level of performance and software transparency needing no additional dedicated program for fault tolerance. To meet these requirements, we propose quadprocessor redundancy (QPR) architecture that combines dualRISC based duplicated CPUs integrating main memories, and duplicated I/O subsystems by using some additional hardware. Duplicated CPUs run under the instruction level synchronization (lock step operation) , and the duplicated I/O subsystems are managed by an operating system. When a fault is detected, the faulty CPU is isolated by hardware. User program is continuously executed by the remaining CPU. We applied the QPR to our UNIX servers, and achieved satisfactory levels of performance.