Embedded System Cost Optimization via Data Path Width Adjustment

Barry SHACKLEFORD  Mitsuhiro YASUDA  Etsuko OKUSHI  Hisao KOIZUMI  Hiroyuki TOMIYAMA  Akihiko INOUE  Hiroto YASUURA  

IEICE TRANSACTIONS on Information and Systems   Vol.E80-D    No.10    pp.974-981
Publication Date: 1997/10/25
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High Level Synthesis
embedded systems,  system on chip,  CPU,  memory,  

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Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator, we show that there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.