Generating Random Benchmark Circuits with Restricted Fan-Ins

Kazuo IWAMA  Kensuke HINO  Hiroyuki KUROKAWA  Sunao SAWADA  

IEICE TRANSACTIONS on Information and Systems   Vol.E80-D   No.10   pp.1009-1016
Publication Date: 1997/10/25
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Design
logic optimization,  benchmark circuits,  random benchmarking,  

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Our basic idea of generating random benchmark circuits, i.e., not generating them directly but applying random transformations to initial circuits was presented at DAC'94. In this paper we make the two major improvements towards the goal of random benchmarking: i.e., increasing the generality, the naturality, the security of random circuits: One is controlling fan-ins of logic gates in the random circuits, and the other is producing the initial circuit also at random but under some control of its on-set size and complexity. Experimental data claiming merits of those improvements are also given.