A Low Voltage High Speed Self-Timed CMOS Logic for the Multi-Gigabit Synchronous DRAM Application

Hoi-Jun YOO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.8   pp.1126-1128
Publication Date: 1997/08/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Integrated Electronics
Keyword: 
low voltage,  self-timed CMOS logic,  synchronous DRAM,  

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Summary: 
A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.