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A Low Voltage High Speed Self-Timed CMOS Logic for the Multi-Gigabit Synchronous DRAM Application
IEICE TRANSACTIONS on Electronics
Publication Date: 1997/08/25
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Integrated Electronics
low voltage, self-timed CMOS logic, synchronous DRAM,
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A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.