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Self-Learning Analog Neural Network LSI with High-Resolution Non-Volatile Analog Memory and a Partially-Serial Weight-Update Architecture
Takashi MORIE Osamu FUJITA Kuniharu UCHIMURA
IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Neural Networks and Chips
neural networks, analog LSI, floating gate device, non-volatile memory,
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A self-learning analog neural network LSI with non-volatile analog memory which can be updated with more than 13-bit resolution has been designed, fabricated and tasted for the first time. The non-volatile memory is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance. We also propose a partially-serial weight-update architecture in which the plural synapse circuits use a weight-update circuit in common to reduce the circuit area. A prototype chip fabricated using a 1.3-µm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weights can be updated at a rate of up to 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.