Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing

Takahiro HANYU  Manabu ARAKAKI  Michitaka KAMEYAMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.7   pp.948-955
Publication Date: 1997/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multiple-Valued Architectures
Keyword: 
logic value conversion (LVC),  floating-gate MOS transistor,  threshold operation,  single-transistor cell,  fully parallel template matching,  

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Summary: 
This paper presents a 4-valued content-addressable memory (CAM) for fully parallel template-matching operations in real-time cellular logic image processing with fixed templates. A universal literal is essential to perform a multiple-valued template-matching operation. It is decomposed of a pair of a threshold operation in a CAM cell and a logic-value conversion shared by CAM cells in the same column of a CAM cellular array, which makes a CAM cell function simple. Since a threshold operation together with a 4-valued storage element can be designed by using a single floating-gate MOS transistor, a high-density 4-valued universal-literal CAM with a single-transistor cell can be implemented by using a multi-layer interconnection technology. It is demonstrated that the performance of the proposed CAM is much superior to that of conventional CAMs under the same function.