Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control

Takahiro HANYU  Satoshi KAZAMA  Michitaka KAMEYAMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.7   pp.941-947
Publication Date: 1997/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multiple-Valued Architectures
Keyword: 
54-bit multiplier,  signed-digit arithmetic,  differential logic circuit,  threshold detector,  source-coupled pair,  multi-phase clocking,  

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Summary: 
A new multiple-valued current-mode (MVCM) integrated circuit using a switched current-source control technique is proposed for a 1.5 V-supply high-speed arithmetic circuit with low-power dissipation. The use of a differential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In the proposed DLC using a switched current control technique, the static power dissipation can be greatly reduced because current sources in non-active circuit blocks are turned off. Since the gate of each current source is directly controlled by using a multiphase clock whose technique has been already used in dynamic circuit design, no additional transistors are required for currentsource control. As a typical example of arithmetic circuits, a new 1.5 V-supply 5454-bit multiplier based on a 0.8µm standard CMOS technology is also designed. Its performance is about 1.3 times faster than that of a binary fastest multiplier under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the proposed MVCM integrated circuit.