Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis

Ho-Yup KWON  Koji KOTANI  Tadashi SHIBATA  Tadahiro OHMI  

IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.7   pp.924-930
Publication Date: 1997/07/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Novel Concept Devices
neuron MOS,  deep-threshold,  low power,  full adder,  number detector,  

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The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.