For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
SOI/CMOS Circuit Design for High-Speed Communication LSIs
Kimio UEDA Yoshiki WADA Takanori HIROTA Shigenobu MAEDA Koichiro MASHIKO Hisanori HAMANO
IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Novel Structure Devices
multiplexer, demultiplexer, CMOS device, SOI/CMOS device, low-power, high-speed,
Full Text: PDF(558.1KB)>>
This paper discusses the features of SOI/CMOS circuits in comparison with bulk/CMOS circuits. We have to design circuits with small fan outs and short wires to take advantage of high-speed and low-power SOI/CMOS devices to their fullest. We can take advantage of the SOI/CMOS structure if the ratio of the source/drain capacitances to the gate capacitances is much greater in the load capacitance. Thus, we propose a new flip-flop circuit with a smaller gate capacitance. The flip-flop circuit operates 30% faster than the previous circuit at 2.0 V. We also propose a buffer circuit having less delay disparity between the complementary output signals. The buffer circuit has the delay disparity of 18 ps at 0.2 pF and 2.0 V. We fabricated an 8-bit frequency divider and a 4-bit demultiplexer using the proposed circuits and 0.35 µm SOI/CMOS process. The 8-bit frequency divider and the 4-bit demultiplexer operate at 2.8 GHz and 1.6 GHz, respectively, at 2.0 V.