A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs

Kiyohiro FURUTANI  Tsukasa OOISHI  Mikio ASAKURA  Hideto HIDAKA  Hideyuki OZAKI  Michihiro YAMADA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E80-C    No.4    pp.582-589
Publication Date: 1997/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
DRAM,  test,  redundancy,  

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Summary: 
This paper proposes a new test mode circuit which enables the massively parallel test of DRAMs with a standard LSI tester with little chip area penalty. It is useful to enhance the test throughput that can't be improved by the conventional multi-bit test mode. And a new redundancy circuit that detects and repairs the short circuit failures in the memory cell array is also proposed. It greatly improves the yield of super low power 256 Mbit DRAMs.