A 5.8 ns 256 kb SRAM with 0.4 µm Super-CMOS Process Technology

Kunihiko KOZARU  Atsushi KINOSHITA  Tomohisa WADA  Yutaka ARITA  Michihiro YAMADA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.4   pp.566-572
Publication Date: 1997/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
super-CMOS,  high-speed SRAM,  reference voltage generator,  voltage down converter,  

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Summary: 
This paper presents Super-CMOS SRAM process technology that integrates bipolar and CMOS transistors in a chip while adding only one ion implantation step and no lithography mask steps to the conventional CMOS SRAM process. The Super-CMOS SRAM process therefore has the same process cost as the CMOS SRAMs, while it achieves higher access speeds. In order to demonstrate the Super-CMOS SRAM, we have developed a 3.3 V/5 V 256 kb SRAM using 0.4 µm Super-CMOS process technology. By applying bipolar transistors to the sense amplifier circuits, a high-speed access time of 5.8 ns with a 3.0 V power supply is successfully achieved.