A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM

Hideharu YAHATA  Yoji NISHIO  Kunihiro KOMIYAJI  Hiroshi TOYOSHIMA  Atsushi HIRAISHI  Yoshitaka KINOSHITA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.4   pp.557-565
Publication Date: 1997/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
CMOS,  high speed,  cache SRAM,  chip floor plan,  sense amplifier,  output register,  setup/hold time,  

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Summary: 
A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-µm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5 V and an ambient temperature of 75. The same margins 1.1 ns of the setup time and hold time were measured for the specifications of a setup time of 2.0 ns and a hold time of 0.5 ns.