Hierarchical Word-Line Architecture for Large Capacity DRAMs

Tatsunori MUROTANI  Tadahiko SUGIBAYASHI  Masahide TAKADA  

IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.4   pp.550-556
Publication Date: 1997/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: Memory LSI
DRAM,  hierarchical word line,  partial subarray activation,  

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The number of DRAMs that have adopted hierarchical word-line architecture has increased as developed DRAM memory capacity has increased to more than 64 Mb. Use of the architecture enhances many kinds of DRAM performances, such as access time and fabrication process margin. However, the architecture does cause some problems. This paper describes some kinds of hierarchical word-line circuitries that have been proposed. It also describes a partial subarray activation scheme that is combined with hierarchical word-line and data-line architectures and discusses their potential and required specifications for future multi-giga bit DRAMs.