Compact Realization of Phase-Locked Loop Using Digital Control

Masanori IZUMIKAWA  Masakazu YAMASHINA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.4   pp.544-549
Publication Date: 1997/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
phase-locked loop (PLL),  digital control,  D/A converter,  

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Summary: 
This paper describes a phase-locked loop (PLL) with digital control featuring a binary quantizing circuit, a synchronizing algorithm, a lock detector and a compact D/A converter. The binary quantizing circuit and synchronizing algorithm make it possible to compare phase and frequency together and to reduce digital control logic by half. Interpolation of upper-bit D/A converter output by lower-bit output reduces the number of current sources of a 9 bit D/A converter from 511 to 80. SPICE simulation with a 0.25 µm CMOS has demonstrated that the development of 200 MHz PLL using digital control is feasible.