Circuit Technology for Giga-bit/Low Voltage Operating SOI-DRAM

Akihiko YASUOKA  Kazutami ARIMOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.3   pp.436-442
Publication Date: 1997/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on SOI Devices and Their Process Technologies)
Category: Circuit Technologies and Applications
Keyword: 
low voltage operation,  SOI-DRAM,  body control,  long data retention time,  high speed,  

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Summary: 
The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.