An Advanced Shallow SIMOX/CMOS Technology for High Performance Portable Systems

Alberto O. ADAN
Toshio NAKA
Seiji KANEKO
Daizo URABE
Kenichi HIGASHI
Yasumori FUKUSHIMA
Soshu TAKAMATSU
Shogo HIDESHIMA
Atsushi KAGISAWA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E80-C    No.3    pp.407-416
Publication Date: 1997/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on SOI Devices and Their Process Technologies)
Category: 
Keyword: 
SOI,  SIMOX,  CMOS,  low-power,  high-speed,  

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Summary: 
A 0.35 µm CMOS process for low-voltage, high-performance applications implemented in an ultra-thin-film SIMOX wafer: Shallow SIMOX, is described. Fully Depleted CMOS devices are realized in a 50 nm thick top Si film. Stable high speed, low-Vth transistors for low-voltage operation were developed by integrating a salicided dual gate process. Short-channel effects are suppressed by a novel channel-drain profile engineering. Low power consumption is achieved by the reduced diffusion capacitance of the SIMOX device and a thick, CMP planarized, intermetal dielectric to reduce metal interconnect capacitance's. Compared with the Bulk-Si CMOS devices, a factor of 1/5 reduction on power dissipation is achieved with this technology. A high ESD strength of 4 kV (HBM) demonstrates the applicability of this technology in advanced high-performance products.