Physical Modeling Needed for Reliable SOI Circuit Design

Jerry G. FOSSUM  Srinath KRISHNAN  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.3   pp.388-393
Publication Date: 1997/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on SOI Devices and Their Process Technologies)
Category: Device and Process Technologies
Keyword: 
SOI,  compact models,  circuit simulation,  floating-body,  

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Summary: 
Physical models for fully depleted (FD) and non-fully depleted (NFD) SOI MOSFETs are overviewed, and recent applications of them (in SOISPICE) are described, stressing the need for good physics-based accounting for the inherently coupled bipolar and MOS device features in reliable circuit design. The applications suggest that asymmetrical double-gate FD/SOI CMOS technology can be scaled below 0.1 µm, whereas the single-gate counterpart seemingly cannot be, and that the floating-body charge dynamics and the associated transient leakage current in NFD/SOI (and FD/SOI) pass transistors in memory (DRAM and SRAM) circuits can be effectively controlled by optimal device design.