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A Low Power CMOS Dual Modulus Prescaler for Frequency Synthesizers
Francesco PIAZZA Qiuting HUANG
IEICE TRANSACTIONS on Electronics
Publication Date: 1997/02/25
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
low power CMOS, communications, frequency synthesis,
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A low power dual modulus prescaler for frequency synthesizers has been designed in a standard 1.2 µm digital CMOS process using enhancement source coupled logic (ESCL). Being a differential low amplitude current mode logic, ESCL has two interesting characteristics for this design besides low power consumption: the low noise performance, that allows this circuit to be on the same chip with sensitive analog circuitry, and the ability to run with a 200 mV sinusoidal signal as generated from an LC oscillator without the need of a clock amplifier. At 195 MHz and 3 V supply, the current consumption of the prescaler is as low as 289 µA, while maximum operating frequencies of 910 MHz at 5 V and 650 MHz at 3 V are achieved.