A Switched Virtual-GND Level Technique for Fast and Low Power SRAM's

Nobutaro SHIBATA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.12   pp.1598-1607
Publication Date: 1997/12/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
SRAM,  low power,  virtual GND,  column address,  synchronous,  macrocell,  

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Summary: 
Fast and low-power circuit techniques suitable for size-configurable SRAM macrocells are described. An SRAM cell architecture using virtual-GND lines along bitlines is proposed; each virtual-GND line switches the potential by inner read-enable and column-address-decoded signals. Reducing the active power dissipation in the memory array and shortening the time for writing data are simultaneously accomplished. The range of available supply voltages is enhanced by adoptive higher virtual-GND level control with a simple voltage limiter. An SRAM-macrocell test chip is designed and fabricated with 0.5-µm CMOS technology. A 4K-word6-bit organization SRAM demonstrates 186-MHz operation at a 3.3-V typical power supply. Its power dissipation at a practical operating frequency, 100-MHz, is reduced to 29% (25-mW) by the proposed virtual-GND line techniques.