For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO
Masayuki MIZUNO Koichiro FURUTA Takeshi ANDOH Akira TANABE Takao TAMURA Hidenobu MIYAMOTO Akio FURUKAWA Masakazu YAMASHINA
IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
phase-locked loop, low voltage, low jitter, fast-lock time,
Full Text: PDF>>
Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication systems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficult because the increase in loop stability needed to reduce jitter increases the lock time. The second is the problem caused by circuits operating at low voltage supplies. Low voltage supplies adversely effect the performance of phase-frequency detectors and charge pump circuits, and they can decrease the noise immunity of oscillators. We have developed a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techniques, such as a noise-immune adaptive-gain voltage-controlled oscillator, for a fabricated PLL. This PLL is fully integrated onto a 480-µm450-µm die area with 0.18-µm CMOS technology. It can operate from 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0.5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.