Vdd=3.0 V) power consumption. The differential linearity error of less than +/-1 LSB is obtained." />

A 10-bit 50 MS/s 300 mW A/D Converter Using Reference Feed-Forward Architecture

Takashi OKUDA  Osamu MATSUMOTO  Toshio KUMAMOTO  Masao ITO  Hiroyuki MOMONO  Takahiro MIKI  Takeshi TOKUDA  

IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.12   pp.1553-1559
Publication Date: 1997/12/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
pipelined A/D converter,  reference feed-forward architecture,  offset cancellation technique,  gain matching,  

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This paper describes the 10-bit 50 MS/s pipelined CMOS A/D Converter using a "reference feed-forward architecture." In this architecture, reference voltage generated in a reference generator block and residual voltage from a DA/subtractor block are fed to the next stage. The reference generator block and DA/subtractor block are constructed using resistive-load, low-gain differential amplifiers. The high-gain, high-speed amplifiers consuming much power are not used. Therefore, the power consumption of this ADC is reduced. The gain matching of the reference voltage with the internal signal range is achieved through the introduction of the reference generator block having the same characteristics as a DA/subtractor block. Each offset voltage of the differential amplifier in the reference generator block and the DA/subtractor block is canceled by the offset cancellation technique, individually. In addition, the front-end sample/hold circuit is eliminated to reduce power consumption. Because of the introduction of high-speed comparators based on the source follower and latch circuit into the first stage A/D subconverter, analog bandwidth is not degraded. This ADC has been fabricated in double-polysilicon, double-metal, 0.5µm CMOS technology, and it operates at 50 MS/s with a 300-mW (Vdd=3.0 V) power consumption. The differential linearity error of less than +/-1 LSB is obtained.