For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Low-Power Circuit Design Techniques for Si Bipolar Gbit/s LSIsAn Overview
IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Si bipolar, high speed, low power, optical transmission,
Full Text: PDF>>
This paper surveys low-power design techniques for Si bipolar Gbit/s LSIs. First, a total strategy for power reduction in bipolar LSIs is described. The power dissipation of Si bipolar LSIs can be minimized by reducing the supply voltage, switching and driving currents, the power of input and output circuits, and the equivalent "on" ratio. Widely spread activities from device to architecture levels are indispensable and each of the low-power techniques reduces power by a factor of about 0.5 to 0.7. The integration of these techniques is very important, and as a certain example of their effectiveness, an SOH signal processing LSI is demonstrated with a reduction factor of 1/10. Comparisons with other device technologies for low power characteristics reveal the low-power potential of bipolar LSIs in the Gbit/s region.