For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Parallel mB1C Word Alignment Procedure and Its Performance for High-Speed Optical Transmission
Yoshihiko UEMATSU Koichi MURATA Shinji MATSUOKA
IEICE TRANSACTIONS on Communications
Publication Date: 1997/03/25
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Communication Systems and Transmission Equipment
mBlC code, DmB1M code, word alignment, parallel processing, signal flow graph,
Full Text: PDF(556.4KB)>>
This paper proposes a parallel word alignment procedure for m Binary with 1 Complement Insertion (mBlC) or Differential m Binary with l Mark Insertion (DmBlM) line code. In the proposed procedure for mBlC line code, the word alignment circuit searches (m+1) bit pairs in parallel for complementary relationships. A Signal Flow Graph Model for the parallel word alignment procedure is also proposed, and its performance attributes are numerically analyzed. The attributes are compared with those of the conventional bit-by-bit procedure, and it is shown that the proposed procedure displays superior performance in terms of False-Alignment Probability and Maximum Average Aligning Time. The proposed procedure is suitable for high speed optical data links, because it can be easily implemented using a parallel signal processor operating at a clock rate equal to 1/(m+1) times the mBlC line rate.