Efficient Timing Verification of Latch-Synchronized Systems

Sang-Yeol HAN  Young Hwan KIM  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E80-A       pp.1676-1683
Publication Date: 1997/09/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Category: VLSI Design Technology and CAD
Keyword: 
VLSI design,  synchronous elements,  critical path analysis,  timing error,  

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Summary: 
This paper presents an event-driven approach to the timing verification of latch-synchronized systems. The proposed method performs critical path extraction and timing error detection at the same time, and extracts the critical path only if necessary. By doing so, the complexity of analysis is reduced and efficiency is greatly improved over the conventional approaches which detect timing errors after extracting the complete critical paths of the system. Experimental results show that, compared to the existing methods, it provides a more than 12-fold improvement in speed on the average for ISCAS benchmark circuits, and the relative efficiency of analysis improves as the circuit size grows.