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Spare Allocation and Compensation-Path Finding for Reconfiguring WSI Processor Arrays Having Single-Track Switches
Takao OZAWA Takeshi YAMAGUCHI
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/06/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
WSI processor array, processor array reconfiguration, fault tolerant computer systems,
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In contrast to previous algorithms for reconfiguring processor arrays under the assumption that spare rows and columns are placed on the perimeter of the array or on fixed positions, our new algorithm employs movable and partitionable spare rows and columns. The objective of moving and partitioning spare rows and/or columns is the elimination of faulty processors each of which is blocked in all directions to spare processors. The results of our computer simulation indicate that reconfigurability can significantly be improved.