A Synchronous Completion Prediction Adder (SCPA)

Jeehan LEE  Kunihiro ASADA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E80-A   No.3   pp.606-609
Publication Date: 1997/03/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: VLSI Design Technology and CAD
adder,  CLA,  completion prediction,  completion detection,  

Full Text: PDF(228KB)>>
Buy this Article

In this paper, a novel completion prediction adder is proposed. The basic concept is to predict the completion of an adder by investigating the inputs and generate completion signal for synchronization according to the completion prediction signal. This scheme greatly enhances the performance of an adder in both aspects of delay and hardware cost. Furthermore, the relative performance enhancement compared with representative synchronous adders increases as the word length of an adder becomes longer. For example, the delay-hardware product of SCPA for a 64-bit adder is 45.1% and 42.7% of those of binary carry look-ahead adder (BCLA) and binary tree carry look-ahead adder (BTCLA), respectively.