Inverter Reduction Algorithm for Super Fine-Grain Parallel Processing

Hideyuki ITO  Kouichi NAGAMI  Tsunemichi SHIOZAWA  Kiyoshi OGURI  Yukihiro NAKAMURA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E80-A   No.3   pp.487-493
Publication Date: 1997/03/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
super fine-grain parallel processing,  FPGA,  high level synthesize PARTHENON,  inverter reduction,  dynamical system,  

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We are working on an algorithm to optimize the logic circuits that can be realized on the super fine-grain parallel processing architecture. As a part of this work, we have developed an inverter reduction algorithm. This algorithm is based on modeling logic circuits as dynamical systems. We implement the algorithm in the PARTHENON system, which is the high level synthesis system developed in NTT's laboratories, and evaluate it using ISCAS85 benchmarks. We also compare the results with both the existing algorithm of PARTHENON and the algorithm of Jain and Bryant.