Experimental Analysis of Power Estimation Models of CMOS VLSI Circuits

Tohru ISHIHARA  Hiroto YASUURA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E80-A   No.3   pp.480-486
Publication Date: 1997/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
CMOS VLSI circuits,  low power design,  power estimation,  

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Summary: 
In this paper, we discuss on accuracy of power dissipation medels for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with power consumption of actual VLSI chips. To evaluate the accuracy of several kinds of power dissipation models in chip-level, block-level and gate-lebel etc., we have been (i) Measuring power consumtion of actual microprocessors, (ii) Estimating power consumption with several kinds of power dissipation models, and (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate. (3) Area of each functional block is a good approximation of load capacitance of the block.