IEICE Trans - PLL Frequency Synthesizer for Low Power Consumption

PLL Frequency Synthesizer for Low Power Consumption

Yasuaki SUMI  Kouichi SYOUBU  Kazutoshi TSUDA  Shigeki OBOTE  Yutaka FUKUI

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E80-A    No.3    pp.461-465
Publication Date: 1997/03/25
Online ISSN:
DOI:
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category:
Keyword:
low power consumption,  PLL frequency synthesizer,  frequency extender,  programmable divider,  operating frequency,  prescaler,

Full Text: PDF>>

Summary:
In this paper, in order to achieve the low power consumption of programmable divider in a PLL frequency synthesizer, we propose a new prescaler method for low power consumption. A fixed prescaler is inserted in front of the (N +1/2) programmable divider which is designed based on the new principle. The divider ratio in the loop does not vary at all even if such a prescaler is utilized. Then the permissible delay periods of a programmable divider can be extended to two times as long as the conventional method, and the low power consumption and low cost in a PLL frequency synthesizer have been achieved.