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Track/Hold Circuit in GaAs HBT Process
Tsutomu TOBARI Haruo KOBAYASHI Kenji UCHIDA Hiroyuki MATSUURA Mineo YAMANAKA Shinji KOBAYASHI Tadashige FUJITA Akira MIURA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
track-hold, sample-hold, analog-to-digital converter, HBT, GaAs,
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This paper reports on the design and performance of a very fast Track/Hold (T/H) circuit with GaAs Heterojunction Bipolar Transistor (HBT) to precede a 3GS/s 6 bit ADC. The T/H circuit employs a differential open-loop architecture for high-speed operation, and it consists of diode bridge switches, hold capacitors and output buffers. The differential structure as well as the output buffers suppress droop effects due to the small hFE (20) of our HBT. Measured results show that the T/H circuit has better than 6 bit linearity within an input range of 1.0 Vp-p with power dissipation of 990m W, and the bandwidth is 6 GHz in the track mode. The measured droop rate is 2.1mV/ns, the feedthrough is -46 dB 500 MHz and the hold pedestal is less than 10m V. Also a 3 GHz sampling operation of the T/H circuit was measured. The T/H circuit uses 43 HBTs, 24 Schottky barrier diodes and occupies a chip area of 1.4 1.75 mm2. We also describe the design and performance of a variable, gain amplifier with GaAs HBT to precede the T/H circuit as an input buffer and adjust its gain. These results support the possibility of meeting the requirements for a high-speed ADC system.