A Built-In Self-Test for ADC and DAC in a Single-Chip Speech CODEC

Eiichi TERAOKA  Toru KENGAKU  Ikuo YASUI  Kazuyuki ISHIKAWA  Takahiro MATSUO  Hideyuki WAKADA  Narumi SAKASHITA  Yukihiko SHIMAZU  Takeshi TOKUDA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E80-A   No.2   pp.339-345
Publication Date: 1997/02/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
Category: 
Keyword: 
built-in self-test,  CODEC,  digital signal processor,  

Full Text: PDF>>
Buy this Article




Summary: 
Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The eight performance characteristics of the ADC and the DAC designed in accordance with the ITU-T recommendations are measured using the BIST. Three of the eight characteristics - the attenuation/frequency distortion, the variation of gain with input level, and the signal-to-total distortion - have been evaluated and the measured results have shown good agreement with measured results by conventional tests. In the BIST operation, the DSP-core generates input stimulus and analyzes output response by control of the self-test program, The sizes of the self-test program and coefficient data are 822 words of the IROM and 384 words of the data ROM, respectively. This area overhead is less than 0.5% of total chip area. Test-time by the BIST is reduced to approximately 3.2 seconds, which is one-tenth that of conventional testing. The mixed-signal DSP-core ASIC is testable with only logic test equipment, and as a result, test-cost - that is test investment and test-time - is reduced compared with conventional test methods.